--cpld training sample no.1 19/7/18

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library ARITHMETIC;
use ARITHMETIC.std_logic_arith.all;

entity trngsmpl1 is
PORT (
		SEGOUT:out std_logic_vector(7 downto 0);
		LEDOUT:out std_logic_vector(3 downto 0);
		SWA:in std_logic;
		SWB:in std_logic;
		SWC:in std_logic;
		PA:out std_logic_vector(7 downto 0);
		PB:out std_logic_vector(7 downto 0);
		PCL:out std_logic_vector(3 downto 0);
		PCH:out std_logic_vector(3 downto 0));
end trngsmpl1;

architecture rtl of trngsmpl1 is
--
begin
--
SEGOUT<="00000000";
LEDOUT<="0000";
--
process(SWA,SWB,SWC)
begin
	if SWA='0' then
		PA<="00000000";
	else
		PA<="11111111";
	end if;
--
	if SWB='0' then
		PB<="00000000";
	else
		PB<="11111111";
	end if;
--
	if SWC='0' then
		PCL<="0000";
		PCH<="0000";
	else
		PCL<="1111";
		PCH<="1111";
	end if;
end process;
--
end rtl;